Structural Constraints in AI Hardware: HBM Scaling, Materials Engineering, and the role of the EPIC Center
By Markos: Introduction — How We Work at AAIG
First of all let me explain a bit how we work specifically on the HBM market.
At AAIG we don’t start with conclusions. We start with a tailored structure for each research. For the HBM research (which we will release in the next weeks here on the platform) the first step is to determine what actually happened, what signals are embedded in that development, and how those signals fit into the structural frameworks we use to understand the market.
This approach is particularly important in semiconductor research. The headline of a partnership announcement can look pretty simple. But the real significance often sits one or two layers deeper in the supply chain. Once a development is placed inside the broader ecosystem of chip design and manufacturing processes or materials science and packaging technology, the signals reveal where the real differences are forming.
Instead of relying primarily on very static spreadsheet forecasts which are useless in this phase we focus on identifying what actually governs the market. In the complex AI build-out the decisive question is not only how large demand will become. The decisive question is which constraints determine how fast the system can scale.
This is why our HBM research focuses on identifying what we call the governors of the market. These governors include packaging constraints, yield learning cycles, thermal limits, and increasingly the materials layer of semiconductor manufacturing itself. Once those governors are identified, the framework becomes a moving engine. As new developments appear—whether they involve packaging technologies, materials innovations, or research partnerships we can map them back to those governors and determine whether they loosen or reinforce the constraints. This is a critical and differentiating approach in our eyes
The development around Applied Materials’ EPIC Center provides an nice example of this process. The announcement itself is straightforward. But once we place it inside the HBM framework, it begins to reveal something much more important: where the next bottlenecks in the AI infrastructure stack are emerging and time-line on solving those bottlenecks. So let’s get into the EPIC Center developments.
The Development
Applied Materials is building a semiconductor research facility in Silicon Valley called the EPIC Center, short for the Equipment and Process Innovation and Commercialization Center.
The facility represents roughly $5 billion in investment and includes approximately 180,000 square feet of cleanroom space. The goal is to accelerate semiconductor innovation by allowing materials science, process integration, and packaging technologies to be developed simultaneously rather than sequentially. Samsung was the first major participant announced, joining the EPIC ecosystem as a founding member. Its collaboration focuses broadly on patterning technologies, deposition processes, etching innovations, and materials development across both logic and memory technologies.
Shortly afterward, SK hynix joined the EPIC ecosystem through a long-term R&D partnership focused on next-generation DRAM and HBM technologies for AI workloads. The partnership includes work on materials science, advanced packaging, hybrid bonding technologies, and thermal integration challenges. Micron almost at the same time joined as another partner, focusing on DRAM, HBM, NAND, and advanced packaging technologies aimed at improving energy efficiency and bandwidth in AI memory systems. Viewed on the surface, this looks like a collaborative research initiative between equipment vendors and memory manufacturers. But this collaberation has also company specific rules and own IP development
Signals From the Development
Several signals stand out from the EPIC Center partnerships when you dig into the proposition. The first signal is the participation of all three major DRAM manufacturers in the same innovation ecosystem. Samsung, SK hynix, and Micron compete directly in the memory market, particularly in HBM. Their joint presence in the EPIC ecosystem suggests that some of the challenges facing the industry are not purely competitive execution differences but shared manufacturing constraints across the entire ecosystem
The second signal is the strong emphasis on atomic-scale materials engineering. The EPIC Center research programs repeatedly reference innovations in deposition, etching, thin films, and dielectric materials. These processes determine how semiconductor structures are built at the atomic scale. As semiconductor architectures become more complex, the atomic properties of materials increasingly influence performance, reliability, and thermal behavior.
The third signal is the growing importance of advanced packaging technologies. HBM achieves its performance advantage by stacking DRAM dies vertically using Through-Silicon Vias. (TSV) As stack heights increase, packaging precision becomes more difficult. Hybrid bonding technologies promise higher density interconnects but require extremely precise alignment and extremely clean bonding surfaces.
The fourth signal is the increasing relevance of thermal management. Dense memory stacks concentrate heat inside a small area. As HBM generations move toward higher layer counts, managing heat becomes a central engineering challenge. Finally, the EPIC Center highlights the evolving role of equipment companies in semiconductor innovation. Applied Materials is not simply supplying tools. Through EPIC it becomes embedded in the early stages of semiconductor process development. A huge step and signal that show difference on earlier memory cycles and strengthen “this time is different narrative”. I personally hate this quote because it is misused a lot but now it is applicable in my opinion.
Impact on the HBM Governors
To understand why these signals matter, it helps to step back and examine the HBM governors themselves as we do in the full HBM research very thoroughly. HBM scaling is not governed by demand alone. The technology is constrained by a set of physical and manufacturing limits that determine how quickly new generations can be deployed.
One of the most important governors is advanced packaging. HBM stacks rely on TSV technology to connect multiple DRAM dies vertically. As stacks grow taller, alignment precision becomes increasingly difficult and packaging throughput becomes a bottleneck.
Another governor is yield learning. In stacked architectures, a defect in one layer can compromise the entire stack. As the number of layers increases, yield learning cycles become longer and more complex.
Thermal behavior represents a third governor. Dense memory stacks generate significant heat, and managing that heat becomes increasingly difficult as architectures scale.
Finally, the deepest governor sits at the level of materials science. Semiconductor performance increasingly on the properties of the materials themselves, including dielectric behavior, bonding integrity, and thermal conductivity.
Understanding these governors allows us to evaluate how new developments influence the pace of HBM scaling. You will see the full mapping in the big HBM research and how they affect each other. In this article I will lay-out what the deeper impact is from the EPIC center.
How the EPIC Center Directly Affects the HBM Governors
The EPIC Center is designed specifically to address the layers where these governors operate. First, EPIC directly targets the packaging governor. Research into hybrid bonding, advanced interconnect structures, and packaging integration can improve the efficiency and reliability of stacked memory architectures.
Second, the center addresses the yield learning governor by enabling parallel development of materials, process technologies, and equipment optimization. By integrating these elements earlier in the development cycle, manufacturers may reduce the time required to achieve high-yield production.
Third, EPIC research focuses on thermal management solutions. New materials and bonding structures can improve heat dissipation across stacked memory architectures.
Finally, the center emphasizes materials engineering, which sits at the deepest layer of the HBM scaling problem. Atomic-scale improvements in deposition processes, dielectric materials, and bonding interfaces can influence electrical performance, thermal behavior, and long-term reliability. A layer which is massively underlooked by investors which I will talk about later. Viewed through this lens, the EPIC Center is essentially a coordinated attempt to address the exact constraints that govern HBM scaling. A key development which will play a crucial role in scaling and meeting demand at the cutting edge of innovation in AI.
Company Positioning
The EPIC partnerships also reveal how the participating companies are positioning themselves within the AI infrastructure ecosystem.
SK hynix: SK hynix currently leads the HBM market and supplies a large portion of the HBM used in leading AI accelerators. Maintaining that leadership requires continued innovation. Positioning themselves in the EPIC ecosystem allows SK hynix to remain close to the forefront of materials and process innovation.
Samsung: Samsung remains the largest integrated memory manufacturer globally. However, its position in the HBM market has lagged behind SK hynix in recent cycles. The EPIC partnership provides Samsung with access to collaborative process development that may help accelerate improvements in advanced memory packaging and manufacturing execution.
Micron: Micron entered the HBM market later but is rapidly increasing its focus on AI memory technologies. By collaborating with Applied Materials, Micron gains access to advanced materials and process development capabilities that could accelerate its ability to scale HBM production. As the smaller player they can slingshot certain development techniques and keep at the forefront of volume ramps by Nvida.
Applied Materials: Applied Materials is positioning itself beyond the traditional role of an equipment supplier. As noted before this is a huge change. Through EPIC, the company becomes embedded in semiconductor innovation itself, particularly in the materials and process layers that increasingly determine how quickly new semiconductor architectures can scale.
Now I want to talk a bit of the underlying crucial edge that the EPIC center might develop which is still merely unknown to Investors.
The Atomic and Isotopic Layer
A deeper layer of semiconductor innovation sits at the atomic level of materials engineering. Natural silicon contains several isotopes, including silicon-28, silicon-29, and silicon-30. Isotopic purification—particularly enrichment toward silicon-28—can improve thermal conductivity and reduce phonon scattering within the crystal lattice.
These improvements influence how efficiently heat moves through semiconductor materials, which becomes increasingly important in dense architectures such as stacked HBM memory.
This atomic-level perspective is one of the reasons we began exploring isotopic engineering earlier through our ASPI thesis. That research, which includes our management call and written report for members, examines the role of isotopically enriched materials in advanced semiconductor manufacturing. Which is available on the Substack here and in our discord where we provide updates and our AAIG take on it.
Companies operating in this niche may contribute to improving thermal performance and material stability in future semiconductor systems. As power densities increase across AI infrastructure, atomic-scale materials engineering may become an increasingly relevant factor in performance and efficiency. Read our ASPI thesis if you want to know more about this crucial layer.
Keynote: the strategic takeaway in my view
The EPIC Center highlights a structural shift in how semiconductor innovation is likely to evolve over the coming years. In earlier semiconductor cycles, scaling was largely driven by transistor density improvements and lithography advances. Today the challenge has moved into a far more complex layer of the stack where materials science, advanced packaging, and process integration all interact simultaneously. The EPIC model reflects this shift. Instead of the traditional sequential development model—where chip designers create a roadmap and equipment vendors subsequently develop tools to support it—the industry is moving toward a parallel R&D ecosystem. In this model, materials engineers, process engineers, and equipment vendors collaborate earlier in the technology cycle to solve manufacturing problems before they appear in production. This change has important implications for the competitive structure of the semiconductor ecosystem.
First, it reinforces the idea that R&D collaboration is becoming a strategic necessity rather than an optional partnership model. As semiconductor architectures become more complex, solving manufacturing challenges requires expertise that spans multiple layers of the value chain. The EPIC Center effectively creates a shared environment where these interactions can be studied and optimized earlier in the development cycle.
Second, the EPIC ecosystem strengthens the position of Applied Materials as a strategic technology partner rather than merely a supplier of manufacturing tools. By hosting an ecosystem where leading memory manufacturers collaborate directly on materials and process innovation, Applied Materials moves further up the stack in the innovation hierarchy. This shift also introduces a form of ecosystem lock-in. When semiconductor manufacturers co-develop processes with equipment vendors and integrate those processes deeply into their manufacturing flows, switching costs increase significantly. Over time, this can reinforce the position of the equipment vendor within the ecosystem.
Third, the EPIC Center provides a direct but still young insight into how the industry is preparing for the next stage of AI infrastructure scaling between 2026-2028 and beyond. The 2026–2028 window will, in my view, remain highly constrained. In our full HBM research, we treat 2026 to 2028 as a structurally tight phase and see 2028 to 2030 as the potential break window.
The reason is straightforward: the governors we discussed earlier and several others that appear later in the research require meaningful technological progress and sustained capex before they can materially ease the bottlenecks.
But capital alone does not solve most of these constraints. With the exception of wafer capacity, simply throwing money at the problem does not move the needle. Many of these limits sit in technological areas and technological learning in those domains is inherently uneven. It is a bumpy process that cannot simply be bought.
For example, packaging constraints may gradually loosen if hybrid bonding and improved interconnect technologies reach reliable high-volume production. But still, yield learning and manufacturing complexity remain significant challenges. Adding to that, materials engineering improvements in thermal constraints, like innovations in bonding materials and potentially atomic-scale material structures, may help mitigate some of these limitations in thermal constraints, but they are unlikely to eliminate them entirely.
Do you see what patern is forming?
There are so many governors that are critical in scaling HBM, in this constrained but high-paced AI build-out, that the possibility of them aligning all and relieving the constraint is highly unlikely. From all the information that I have currently got together on the sector, there is still no signal that really points that the 2028-beyond window will break the constraint environment. But I will keep monitoring that in my moving HBM engine, which uses a tiered system with validated info by the companies itself as the highest tier, so we can see how the market is moving and evolving in these constraints.
So for investors and industry observers, I will break this into important implications and strategy that we follow at AAIG.
At the memory level, the HBM cycle remains one of the most powerful demand drivers in the semiconductor market. With my previous explanations on how the governors work and will likely be constrained for a while, our current positioning reflects this through a basket strategy focused on Samsung and SK Hynix, capturing the biggest part of server-level memory demand.
In addition, for the advanced materials and manufacturing layer, I pointed out that this opens the door to new areas of research, including atomic-scale materials engineering and isotopic material technologies. For this underlooked layer, we hold a position in ASP Isotopes. This company still needs to show different execution milestones, but also has a lot of different business units that touch medical, nuclear power, and much more.
Finally, the EPIC Center highlights the importance of continuously monitoring where the next bottlenecks may emerge. As I said before, constraints shift from one layer of the stack to another as technology evolves, and multiple constraints at the same time is nothing strange, as you see now with power and memory also.
Going forward, the developments we watch most closely include progress in hybrid bonding technologies and companies who facilitate that, improvements in packaging throughput, and advancing in thermal management solutions. Each of these developments has the potential, in my opinion, to not only alter the pace of HBM scaling, but also create new opportunities within the semiconductor ecosystem.
Thank you all for reading this article and see you on the next one.
Markos.